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74AUP1G97 Datasheet

Low-power configurable multiple function gate

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74AUP1G97
Low-power configurable multiple function gate
Rev. 9 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VTis defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C


NXP Semiconductors Electronic Components Datasheet

74AUP1G97 Datasheet

Low-power configurable multiple function gate

No Preview Available !

NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G97GW 40 C to +125 C SC-88
74AUP1G97GM 40 C to +125 C XSON6
74AUP1G97GF 40 C to +125 C XSON6
74AUP1G97GN 40 C to +125 C XSON6
74AUP1G97GS 40 C to +125 C XSON6
74AUP1G97GX 40 C to +125 C X2SON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
plastic thermal extremely thin small outline package; SOT1255
no leads; 6 terminals; body 1 0.8 0.35 mm
4. Marking
Table 2. Marking
Type number
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
74AUP1G97GX
Marking code[1]
aV
aV
aV
aV
aV
aV
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1. Logic symbol
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74AUP1G97
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 23


Part Number 74AUP1G97
Description Low-power configurable multiple function gate
Maker NXP
Total Page 23 Pages
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