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74F112 Dual J-K negative edge-triggered flip-flop

74F112 Description

INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors P.
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and comple.

74F112 Features

* in order to improve design and supply the best possible product. Thi

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Dual J-K negative edge-triggered flip-flop NXP
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