Datasheet Details
| Part number | 74F112 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 59.08 KB |
| Description | Dual JK Negative Edge-Triggered Flip-Flop |
| Datasheet | 74F112_FairchildSemiconductor.pdf |
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Overview: 74F112 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F112 Dual JK Negative Edge-Triggered.
| Part number | 74F112 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 59.08 KB |
| Description | Dual JK Negative Edge-Triggered Flip-Flop |
| Datasheet | 74F112_FairchildSemiconductor.pdf |
|
|
|
The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs.
Synchronous state changes are initiated by the falling edge of the clock.
Triggering occurs at a voltage level of the clock and is not directly related to the transition time.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74F112 | Dual J-K negative edge-triggered flip-flop | NXP |
 |
74F112 | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP | Texas Instruments |
| Part Number | Description |
|---|---|
| 74F11 | Triple 3-Input AND Gate |
| 74F113 | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F114 | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F10 | Triple 3-Input NAND Gate |
| 74F1056 | 8-Bit Schottky Barrier Diode Array |
| 74F1071 | 18-Bit Undershoot/Overshoot Clamp |
| 74F109 | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F125 | Quad Buffer |
| 74F132 | Quad 2-Input NAND Schmitt Trigger |
| 74F138 | 1-of-8 Decoder/Demultiplexer |