Datasheet Details
| Part number | 74F113 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 59.84 KB |
| Description | Dual JK Negative Edge-Triggered Flip-Flop |
| Datasheet | 74F113_FairchildSemiconductor.pdf |
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Overview: 74F113 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F113 Dual JK Negative Edge-Triggered.
| Part number | 74F113 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 59.84 KB |
| Description | Dual JK Negative Edge-Triggered Flip-Flop |
| Datasheet | 74F113_FairchildSemiconductor.pdf |
|
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|
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and data may be entered.
The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed.
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| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74F113 | Dual J-K negative edge-triggered flip-flops | NXP |
| Part Number | Description |
|---|---|
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