74F114 Description
The 74F114 contains two high-speed JK flip-flops with mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time.
74F114 Key Features
- K X X X h h
- l Outputs Q H L H Q0 L H Q0 Q L H H Q0 H L Q0 H (h) = HIGH Voltage Level L (h) = LOW Voltage Level X = Immate