74F112
Overview
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
| Part | 74F112 |
|---|---|
| Description | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP |
| Manufacturer | Texas Instruments |
| Size | 666.05 KB |
Related Datasheets
- 74F112 — NXP Semiconductors — Dual J-K negative edge-triggered flip-flop
- 74F113 — Fairchild Semiconductor — Dual JK Negative Edge-Triggered Flip-Flop
- 74F114 — Fairchild Semiconductor — Dual JK Negative Edge-Triggered Flip-Flop
- 74F11 — Fairchild Semiconductor — Triple 3-Input AND Gate
- 74F11 — NXP Semiconductors — Triple 3-input NAND gate