74LVC125A Datasheet - NXP

Quad buffer/line driver

74LVC125A Features

* 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard:

* JESD8-7A (1.65 V to 1.95 V)

* JESD8-5A (2.3 V to 2.7 V)

* JES

74LVC125A General Description

The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V c.

74LVC125A Datasheet (162.64 KB)