s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-.

using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it i.

The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3.

74LVC1G53

74LVC1G53-Q100

74LVC1G57-Q100

74LVC1G58

74LVC1G58-Q100

74LVC1G00

74LVC1G00-Q100

74LVC1G02

74LVC1G02-Q100

74LVC1G04

74LVC1G04-Q100

74LVC1G06

74LVC1G06-Q100