74LVC2373A Datasheet | NXP Semiconductors

FEATURES - 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic - Supply voltage range of 2.7V to 3.6V - plies with JEDEC standard no. 8-1A - CMOS low power consumption - Direct interface with TTL levels - High impedance when VCC = 0V - Bushold on all data inputs (74LVCH2373A only) - Integrated 30W damping resistor DESCRIPTION The 74LVC2373A/74LVCH2373A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC2373A/74LVCH2373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are mon to all internal latches. The ‘2373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL t PHL/t PLH CI CPD PARAMETER Propagation delay Dn to Qn LE to Qn Input capacitance Power dissipation capacitance per latch Notes 1, 2 CONDITIONS CL = 50p F VCC = 3.3V TYPICAL 4.4 5.0 5.0 20 UNIT ns p F p F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz;...