* 5 V tolerant inputs for interlacing with 5 V logic
* Supply voltage range from 1.2 V to 3.6 V
* CMOS low power consumption
* Direct interface with TTL levels
* High-impedance when VCC = 0 V
* Complies with JEDEC standard:
* JESD8-7A (1.65 V to 1.95 V)
* JESD8-5A (2.
74LVC240A Datasheet (144.60 KB)
74LVC240A
144.60 KB
Octal buffer/line driver.
74LVC240A Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state Rev. 8 29 November 2011 Product data sheet 1. Ge.
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