74LVC2G125 Datasheet - NXP

Dual bus buffer/line driver

74LVC2G125 Features

* Wide supply voltage range from 1.65 V to 5.5 V

* 5 V tolerant input/output for interfacing with 5 V logic

* High noise immunity

* Complies with JEDEC standard:

* JESD8-7 (1.65 V to 1.95 V)

* JESD8-5 (2.3 V to 2.7 V)

* JESD8-B/JESD36 (2.7 V to 3.6 V)

* ESD protection

74LVC2G125 General Description

The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly to.

74LVC2G125 Datasheet (179.03 KB)