80C554
Overview
This data sheet describes the 6 clock version of the 8xC554. This device is only available in 64L LQFP.
- 83C554-16k bytes ROM
- 80C554-ROMless version
- 87C554-16k bytes EPROM The 87C554 contains a 16k × 8 non-volatile EPROM, a 512 × 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, four-priority-level, nested interrupt structure, an 7-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8xC554 can be expanded using standard TTL compatible memories and logic. In addition, the 8xC554 has two software selectable modes of power reduction-idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue func
