80C554
Description
This data sheet describes the 6 clock version of the 8xC554. This device is only available in 64L LQFP.
Key Features
- 83C554-16k bytes ROM
- 80C554-ROMless version
- 87C554-16k bytes EPROM The 87C554 contains a 16k × 8 non-volatile EPROM, a 512 × 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, four-priority-level, nested interrupt structure, an 7-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8xC554 can be expanded using standard TTL compatible memories and logic. In addition, the 8xC554 has two software selectable modes of power reduction-idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. Optionally, the ADC can be operated in Idle mode. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal, 58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs. Multiply and divide instructions require 3 µs.
- Two standard 16-bit timer/counters
- 512 × 8 RAM, expandable externally to 64k bytes
- Capable of producing eight synchronized, timed outputs
- A 10-bit ADC with seven multiplexed analog inputs
- Fast 8-bit ADC option - 9 µS at 16 MHz
- Two 8-bit resolution, pulse width modulation outputs
- Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs
