* Vertical power DMOS output stage Overload protected up to 85˚C ambient Overload protection by current limiting and overtemperature sensing Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input
BUK107-50GL Datasheet (92.15 KB)
BUK107-50GL
92.15 KB
Powermos transistor logic level topfet.
DISCRETE SEMICONDUCTORS DATA SHEET BUK107-50DL PowerMOS transistor Logic level TOPFET Product specification Supersedes data of September 1994 File un.
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