LPC2927
Overview
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial and communication markets. To optimize system power consumption, the LPC2926/2927/2929 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.
- ARM968E-S processor running at frequencies of up to 125 MHz maximum.
- Multi-layer AHB system bus at 125 MHz with four separate layers.
- On-chip memory:
- Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data TCM (DTCM).
- Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB SRAM.
- 8 kB ETB SRAM also available for code execution and data.
- Up to 768 kB high-speed flash-program memory.
- 16 kB true EEPROM, byte-erasable and programmable.
- Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can be used with the Serial Peripheral Interface (SPI) interfaces and the UARTs, as well as for memory-to-memory transfers including the TCM memories.
- External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus.
