LPC865 Datasheet | NXP Semiconductors

description The LPC86x is an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 60 MHz. The LPC86x supports up to 64 KB of flash memory and 8 KB of SRAM. The peripheral plement of the LPC86x includes a CRC engine, one I2C-bus interface, one I3C-MIPI bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up timer, two Flex Timers (one with full motor control feature ), a DMA, one 12-bit ADC, one analog parator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins. For additional information related to the LPC86x parts, see Section 4. 2. Features and benefits - System: - Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 60 MHz with single-cycle multiplier and fast single-cycle I/O port. - Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). - System tick timer. - AHB multilayer matrix. - Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported only. - Memory: - Up to 64 KB on-chip flash programming memory with 64 Byte page write and erase. - Code Read Protection (CRP). - Up to 8 KB SRAM consisting of contiguous SRAM banks. - Bit-band addressing is supported to permit atomic operations to modify a single bit. - ROM API support: - Boot loader. - Supports Flash In-Application Programming (IAP). - Supports In-System Programming (ISP) through USART. - FRO API. - Digital peripherals: NXP Semiconductors LPC86x 32-bit Arm Cortex-M0+ microcontroller LPC86x Product data sheet - High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits. The GPIO pins are tri-state when power is on. - High-current source...