MIMX8MD6CVAHZAA
Key Features
- Features Feature Quad symmetric Cortex-A53 processors:
- 32 KB L1 Instruction Cache
- 32 KB L1 Data Cache
- Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture:
- 1 MB unified L2 cache
- Support L2 cache RAMs protection with ECC
- Frequency of 1.5 GHz 16 KB L1 Instruction Cache 16 KB L1 Data Cache 256 KB tightly coupled memory (TCM) Two PCI Express Gen2 interfaces Two USB 3.0/2.0 controllers with integrated PHY interfaces Two Ultra Secure Digital Host Controller (uSDHC) interfaces One Gigabit Ethernet controller with support for EEE, Ethernet AVB, and IEEE 1588 Four Universal Asynchronous Receiver/Transmitter (UART) modules Four I2C modules Three SPI modules 32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600 8-bit NAND-Flash eMMC 5.0 Flash SPI NOR Flash QuadSPI Flash with support for XIP GPIO modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Boot ROM (128 KB) On-chip RAM (128 KB + 32 KB) Temperature sensor with programmable trip points Flexible power domain partitioning with internal power switches to support efficient power management i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products, Rev. 3, 04/2021 2 NXP Semiconductors Subsystem Multimedia Security i.MX 8M Dual / 8M QuadLite / 8M Quad introduction Table
- Features (continued) Feature Video Processing Unit:
- 4Kp60 HEVC/H.265 main, and main 10 decoder
- 4Kp60 VP9 decoder
