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NXP Semiconductors Electronic Components Datasheet

MPC5748G Datasheet

Microcontroller

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NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5748G
Rev. 6, 11/2018
MPC5748G Microcontroller
Data Sheet
Features
• 2 x 160 MHz Power Architecture® e200Z4 Dual issue,
32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200Z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores generate single
error correction, double error detection (SECDED)
code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 6 MB on-chip flash supported with the flash
controller
– 3 x flash page buffers (3 port flash controller)
– 768 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• 2x System Memory Protection Unit (SMPU) each with
16 region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routing
interrupts to any CPU
• Multiple crossbar switch architecture for concurrent
access to peripherals, flash, and RAM from multiple
bus masters
MPC5748G
• Boot Assist Flash (BAF) supports internal flash
programming via a serial link (LIN / SCI)
• Analog
– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit
– Three analogue comparators
– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or from the PIT
• Communication
– Four Deserial Peripheral Interface (DSPI)
– Six Serial Peripheral interface (SPI)
– 18 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (IIC)
– One USB OTG Controller (USB_0) and One USB
SPH Controller (USB_1) with ULPI Interface.
– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/
RMII
– 2 x ENET with L2 switch
– Secure Digital Hardware Controller (uSDHC)
– Dual-channel FlexRay Controller
• Audio
– 3 x Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAIs
• Configurable I/O domains supporting FLEXCAN,
LINFlex, Ethernet, USB, MLB, uSDHC and general
I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200Z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200Z4 core(s): NDI per IEEE-ISTO 5001-2008
Class 3+
• 32-channels eDMA controller with multiple transfer
request sources using DMAMUX
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.


NXP Semiconductors Electronic Components Datasheet

MPC5748G Datasheet

Microcontroller

No Preview Available !

• Timer
– 16 Periodic Interrupt Timers (PITs)
– Three System Timer Module (STM)
– Four Software WatchDog Timers (SWT)
– 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and
1149.7 (cJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL compliance
• Multiple operating modes
– Includes enhanced low power operation
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
2
NXP Semiconductors


Part Number MPC5748G
Description Microcontroller
Maker NXP
Total Page 3 Pages
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