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NXP Semiconductors Electronic Components Datasheet

MPC5777M Datasheet

Microcontroller

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NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5777M
Rev. 6, 06/2016
MPC5777M
MPC5777M Microcontroller
Data Sheet
416 TEPBGA
27mm x 27 mm
512 TEPBGA
25 mm x 25 mm
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
– Power Architecture® embedded specification
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
• Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
• Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
• System Integration Unit Lite (SIUL)
• Boot Assist Module (BAM) supports factory programming
using serial bootload through ‘UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be:
– UART/LIN
– CAN
• GTM104 — generic timer module
• Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
• Eight deserial serial peripheral interface (DSPI) modules
• Two Peripheral Sensor Interface (PSI5) controllers
• Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
• Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
• External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.


NXP Semiconductors Electronic Components Datasheet

MPC5777M Datasheet

Microcontroller

No Preview Available !

Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.1 Power supply and reference voltage pins/balls .15
2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16
2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
3.3 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . .23
3.4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .27
3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.6.1 I/O input DC characteristics . . . . . . . . . . . . . . . .31
3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35
3.7 I/O pad current specification . . . . . . . . . . . . . . . . . . . . .42
3.8 Reset pad (PORST, ESR0) electrical characteristics . .45
3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53
3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54
3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.12 LVDS Fast Asynchronous Serial Transmission
(LFAST) pad electrical characteristics . . . . . . . . . . . . .67
3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68
3.12.2 LFAST and MSC/DSPI LVDS interface
electrical characteristics . . . . . . . . . . . . . . . . . .69
3.12.3 LFAST PLL electrical characteristics . . . . . . . . .72
3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73
3.14 Power management: PMC, POR/LVD, sequencing . . .75
3.14.1 Power management electrical characteristics . .75
3.14.2 Power management integration . . . . . . . . . . . . 75
3.14.3 3.3 V flash supply . . . . . . . . . . . . . . . . . . . . . . . 76
3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77
3.14.5 Power up/down sequencing . . . . . . . . . . . . . . . 79
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80
3.15.1 Flash memory program and erase
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.15.2 Flash memory FERS program and
erase specifications . . . . . . . . . . . . . . . . . . . . . 82
3.15.3 Flash memory Array Integrity and Margin
Read specifications . . . . . . . . . . . . . . . . . . . . . 83
3.15.4 Flash memory module life specifications . . . . . 84
3.15.5 Data retention vs program/erase cycles. . . . . . 84
3.15.6 Flash memory AC timing specifications . . . . . . 85
3.15.7 Flash read wait state and address pipeline
control settings . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.16.1 Debug and calibration interface timing . . . . . . . 86
3.16.2 DSPI timing with CMOS and LVDS pads . . . . . 94
3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115
3.16.5 PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.7 External Bus Interface (EBI) Timing . . . . . . . . 119
3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124
3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124
3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125
3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127
3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130
3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132
3.20.1 General notes for specifications at
maximum junction temperature . . . . . . . . . . . 132
4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MPC5777M Microcontroller Data Sheet, Rev. 6
2
NXP Semiconductors


Part Number MPC5777M
Description Microcontroller
Maker NXP
Total Page 3 Pages
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