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MPC8572E Datasheet

PowerQUICC III Integrated Processor

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NXP Semiconductors
Technical Data
Document Number: MPC8572EEC
Rev. 7, 03/2016
MPC8572E PowerQUICC III
Integrated Processor
Hardware Specifications
1 Overview
This section provides a high-level overview of the features
of the MPC8572E processor. Figure 1 shows the major
functional units within the MPC8572E.
1.1 Key Features
The following list provides an overview of the MPC8572E
feature set:
• Two high-performance, 32-bit, Book E-enhanced
cores that implement the Power Architecture®
technology:
— Each core is identical to the core within the
MPC8572E processor.
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. DDR2 and DDR3 SDRAM Controller . . . . . . . . . . . 19
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 28
9. Ethernet Management Interface
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 50
10. Local Bus Controller (eLBC) . . . . . . . . . . . . . . . . . . 53
11. Programmable Interrupt Controller . . . . . . . . . . . . . 65
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 72
16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
17. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . 101
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
21. System Design Information . . . . . . . . . . . . . . . . . . 127
22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 137
23. Document Revision History . . . . . . . . . . . . . . . . . . 139
NXP reserves the right to change the detail specifications as may be required to permit improvements in
the design of its products.
© 2008-2011, 2014, 2016 NXP B.V.


NXP Semiconductors Electronic Components Datasheet

MPC8572E Datasheet

PowerQUICC III Integrated Processor

No Preview Available !

Overview
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte to 4-Gbyte page sizes.
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the MPC8572E performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some
features that this device implements more specifically. An understanding of these differences can
be critical to ensure proper operation.
• 1 Mbyte L2 cache/SRAM
— Shared by both cores.
— Flexible configuration and individually configurable per core.
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
— Global locking and Flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be Flash cleared separately.
— Per-way allocation of cache region to a given processor.
— SRAM features include the following:
– 1, 2, 4, or 8 ways can be configured as SRAM.
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
• e500 coherency module (ECM) manages core and intrasystem transactions
• Address translation and mapping unit (ATMU)
— Twelve local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
2
NXP Semiconductors


Part Number MPC8572E
Description PowerQUICC III Integrated Processor
Maker NXP
Total Page 3 Pages
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