MPC8560 - Integrated Communications Processor Reference Manual

Reset, Clocking, and Initialization Part II e500 Core Complex and L2 Cache e500 Core Complex Overview e500 Register Summary L2 Look-Aside Cache/SRAM Part III Memory and I/O Interfaces e500 Coherency Module DDR Memory Controller Programmable Interrupt Controller I2C Interface Local B

• and Watchpoint Facility I 1 2 3 4 II 5 6 7 III 8 9 10 11 12 13 14 15 16 IV 17 18 19 I 1 2 3 4 II 5 6 7 III 8 9 10 11 12 13 14 15 16 IV 17 18 19 Part I.
• Overview Overview Memory Map Signal.