The MPC8560 is a Integrated Communications Processor Reference Manual.
| Package | BGA |
|---|---|
| Mount Type | Surface Mount |
| Pins | 783 |
| Operating Voltage | 1.3 V |
| Max Voltage (typical range) | 1.35 V |
| Min Voltage (typical range) | 1.25 V |
| Max Frequency | 166 MHz |
| Length | 29 mm |
NXP Semiconductors
Reset, Clocking, and Initialization Part II—e500 Core Complex and L2 Cache e500 Core Complex Overview e500 Register Summary L2 Look-Aside Cache/SRAM Part III—Memory and I/O Interfaces e500 Coherency .
and Watchpoint Facility
I 1 2 3 4
II 5 6 7
III 8 9 10 11 12 13 14 15 16
IV 17 18 19
I 1 2 3 4
II 5 6 7
III 8 9 10 11 12 13 14 15 16
IV 17 18 19
Part I
*Overview Overview Memory Map Signal Descriptions Reset, Clocking, and Initialization
Part II
*e500 Core Complex and L2 Cache e500 Core Complex Over.
Freescale Semiconductor
Freescale Semiconductor Technical Data MPC8540EC Rev. 3.1, 12/2004 MPC8560 Integrated Processor Hardware Specifications The MPC8560 contains a PowerPC™ processor core. The MPC85.
Figure 1 shows the major functional units within the MPC8560. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. © Freescale Semiconductor, Inc., 2004. All rights reserved. Overview DDR SDRAM DDR SDRAM Controller I2C Controller 256KB L2-Cache/ SRAM e500 Coherency Module e500 .
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