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PCK2509S Datasheet

50-150 MHz 1:9 SDRAM clock driver

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INTEGRATED CIRCUITS
PCK2509S
50–150 MHz 1:9 SDRAM clock driver
Product specification
1999 Oct 19
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

PCK2509S Datasheet

50-150 MHz 1:9 SDRAM clock driver

No Preview Available !

Philips Semiconductors
50–150 MHz 1:9 SDRAM clock driver
Product specification
PCK2509S
FEATURES
Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(tphase error – jitter) at 100 to133 MHz = ±50 ps
Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew < 200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of ten outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
Inputs compatible with 2.5 V and 3.3 V ranges
DESCRIPTION
The PCK2509S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLLto precisely align,
in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2509S operates at 3.3 V VCC and is
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine
low-skew, low-jitter copies of CLK. Output signal duty cycles are
adjusted to 50 percent, independent of the duty cycle at CLK. Each
bank of outputs can be enabled or disabled separately via the
control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low,
the outputs are disabled to the logic–low state.
Unlike many products containing PLLs, the PCK2509S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2509S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up
and application of a fixed-frequency, fixed-phase signal at CLK, and
following any changes to the PLL reference or feedback signals. The
PLL can be bypassed for test purposes by strapping AVCC to ground.
The PCK2509S is characterized for operation from 0°C to +70°C.
PIN CONFIGURATION
AGND 1
VCC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
VCC 10
1G 11
FBOUT 12
24 CLK
23 AVCC
22 VCC
21 2Y0
20 2Y1
19 GND
18 GND
17 2Y2
16 2Y3
15 VCC
14 2G
13 FBIN
SW00389
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
24-Pin Plastic TSSOP
0°C to +70°C
ORDER CODE
PCK2509S PW
DRAWING NUMBER
SOT355-1
1999 Oct 19
2 853–2180 22544


Part Number PCK2509S
Description 50-150 MHz 1:9 SDRAM clock driver
Maker NXP
Total Page 10 Pages
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