PDI1394P23BD Datasheet | NXP Semiconductors

FEATURES - Fully supports provisions of IEEE 1394- 1995 Standard for high performance serial bus and the P1394a- 2000 Standard.1 - Interoperable with link-layer controllers using 3.3 V and 5 V supplies - Fully interoperable with Firewire™ and i.LINK™ implementations of the IEEE 1394 Standard.2 - Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies - Full P1394a support includes: - Connection debounce - Arbitrated short reset - Multispeed concatenation - Arbitration acceleration - Fly-by concatenation - Port disable/suspend/resume - Node power class information signaling for system power management - Cable power presence monitoring - Power down features to conserve energy in battery-powered applications include: - Automatic device power down during suspend - Device power down terminal - Link interface disable via LPS - Inactive ports powered-down - Provides two 1394a fully-pliant cable ports at 100/200/400 Mbps. - Fully pliant with Open HCI requirements - Interface to link-layer controller supports both low-cost bus-holder isolation and optional Annex J electrical isolation - While unpowered and connected to the bus, will not drive TPBIAS on a connected port, even if receiving ining bias voltage on that port - Supports extended bias-handshake time for enhanced interoperability with camcorders - Can be used as a one port PHY without the use of any extra external ponents - Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz - Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbps, and link-layer controller clock at 49.152 MHz - Register bits give software control of contender bit, power class bits, link active bit, and 1394a features - Cable ports monitor line conditions for active connection to remote node. - Does not require external filter capacitors for PLL - LQFP package is function and pin patible with the Texas Instruments TSB41LV02AE™ and TSB41AB2E™ 400 Mbps PHYs. -...