PTN3392 NXP Semiconductors Datasheet

PTN3392 Key Features

• Main Link: 1-lane and 2-lane modes supported
• HBR (High Bit Rate) at 2.7 Gbit/s per lane
• RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
• BER (Bit Error Rate) better than 109
• Down-spreading SSC (Spread Spectrum Clocking) supported
• 1 MHz AUX channel
• Supports native AUX CH syntax
• Supports I2C-bus over AUX CH syntax
• Hot Plug Detect (HPD) signal to the source
• Cost-effective design optimized for VGA application