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SJA1124 Datasheet

Quad LIN master transceiver

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SJA1124
Quad LIN master transceiver with LIN master controller
Rev. 1 — 8 May 2018
Product data sheet
1 General description
The SJA1124 is a quad Local Interconnect Network (LIN) master channel device. Each
of the four channels contains a LIN master controller and LIN transceiver with master
termination. LIN master frames are transferred to the physical LIN bus via the LIN
physical layer. The SJA1124 is primarily intended for in-vehicle subnetworks using
baud rates up to 20 kBd and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A,
ISO 17987-4:2016(12 V LIN) and SAE J2602-1.
A Serial Peripheral Interface (SPI) and an interrupt output provide the interface between
the SJA1124 and a microcontroller.
Transmit data streams received on the SPI are converted by the SJA1124 into LIN
master frames transmitted on the LIN bus. The LIN master frames are transmitted as
optimized bus signals shaped to minimize ElectroMagnetic Emission (EME). The LIN bus
output pins are pulled HIGH via internal LIN master termination resistors. Data streams
received on the LIN bus input pins can be read by the microcontroller via the SPI.
Power consumption is very low in Low Power mode. However, the SJA1124 can still be
woken up via the LIN pins and the SPI interface.
2 Features and benefits
2.1 General
Four LIN master channels:
LIN master controller
LIN transceiver
LIN master termination consisting of a diode and a 1 kΩ ±10 % resistor
Compliant with:
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
ISO 17987-3:2016, ISO 17987-4:2016 (12 V LIN)
SAE J2602-1
Very low current consumption in Low Power mode with wake-up via SPI or LIN
Option to control an external voltage regulator via the INHN output
Bus signal shaping optimized for baud rates up to 20 kBd
SPI for communicating with the microcontroller:
SPI used for configuration, control, diagnosis and LIN data transfer
Flexible SPI length from 3 bytes to 18 bytes
Output status pin signals SPI operational state
Interrupt output pin: interrupts can be configured individually
Facilitates synchronous LIN frame transmission across multiple SJA1124 devices
VIO input for direct interfacing with 3.3 V and 5 V microcontrollers


NXP Semiconductors Electronic Components Datasheet

SJA1124 Datasheet

Quad LIN master transceiver

No Preview Available !

NXP Semiconductors
SJA1124
Quad LIN master transceiver with LIN master controller
On-chip Phase-Locked Loop (PLL) for LIN master controller
Passive behavior in unpowered state
Undervoltage detection
Leadless DHVQFN24 package (3.5 mm × 5.5 mm) supporting improved Automated
Optical Inspection (AOI) capability
2.2 LIN master controllers
Independent per LIN channel:
Baud rate
Operating mode
Status and interrupt
Complete LIN frame handling and transfer
One interrupt per LIN frame
Slave response timeout detection
Programmable break length
Automatic sync field generation
Programmable stop bit length
Hardware parity generation
Hardware or software checksum generation
Fault confinement
Fractional baud rate generator
2.3 Protection
Excellent ElectroMagnetic Immunity (EMI)
Very high ESD robustness: ±6 kV according to IEC61000-4-2 for pins LIN1 to LIN4 and
BAT
Bus terminal and battery pin protected against transients in the automotive environment
(ISO 7637)
Bus terminal short-circuit proof to battery and ground
LIN dominant timeout function
Thermal protection
3 Ordering information
Table 1. Ordering information
Type number Package
Name
Description
SJA1124AHG
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm
Version
SOT 815-1
SJA1124
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 May 2018
© NXP B.V. 2018. All rights reserved.
2 / 54


Part Number SJA1124
Description Quad LIN master transceiver
Maker NXP
Total Page 3 Pages
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