TDA8768AH Datasheet | NXP Semiconductors

Description The TDA8768AH is a bi CMOS 12-bit Analog-to-Digital Converter (ADC) optimized for GSM and EDGE cellular infrastructures, professional telemunications and imaging, and advanced FM radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS patible and all outputs are CMOS patible. A sine wave clock input signal can also be used. 2. Features s 12-bit resolution s Sampling rate up to 70 MHz s - 3 d B bandwidth of 245 MHz s 5 V power supplies and 3.3 V output power supply s Binary or twos plement CMOS outputs s In-range CMOS patible output s TTL and CMOS patible static digital inputs s TTL and CMOS patible digital outputs s Differential AC or PECL clock input; TTL patible s Power dissipation 550 m W (typical) s Low analog input capacitance (typical 2 p F), no buffer amplifier required s Integrated sample-and-hold amplifier s Differential analog input s External amplitude range control s Voltage controlled regulator included s - 40 °C to +85 °C ambient temperature. 3. Applications s High-speed analog-to-digital conversion for: x Cellular infrastructure (GSM and EDGE) x Professional telemunication x Advanced FM radio x Radar x Imaging (camera scanner) x Set Top Box (STB) x Medical imaging. Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 4. Quick reference data Table 1: Symbol VCCA VCCD VCCO ICCA ICCD ICCO DNL f CLK(max) Ptot Quick reference data Parameter Conditions analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity (no missing code) maximum clock frequency f CLK = 20 MHz fi = 400 k Hz f CLK = 20 MHz fi = 400 k Hz f CLK = 20 MHz fi = 400 k Hz TDA8768AH/4 TDA8768AH/5 TDA8768AH/7 total power dissipation f CLK = 55 MHz fi = 20 MHz 5. Ordering information Table 2: Ordering...