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TDA8768H - 12-bit high-speed Analog-to-Digital Converter ADC

Download the TDA8768H datasheet PDF. This datasheet also covers the TDA8768 variant, as both devices belong to the same 12-bit high-speed analog-to-digital converter adc family and are provided as variant models within a single manufacturer datasheet.

Description

The TDA8768 is a bipolar 12-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging.

It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 MHz.

Features

  • 12-bit resolution.
  • Sampling rate up to 55 MHz.
  • 3 dB bandwidth of 190 MHz.
  • 5 V power supplies.
  • Binary or twos-complement CMOS outputs.
  • In-range CMOS-compatible output.
  • TLL-CMOS compatible static digital inputs.
  • 3 to 5 V CMOS-compatible digital outputs.
  • Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible.
  • Power dissipation 325 mW (typical).
  • Low analog input capacitanc.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TDA8768_PhilipsSemiconductors.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NXP Semiconductors

Part Number Description
TDA8768 12-bit high-speed Analog-to-Digital Converter ADC
TDA8768A Analog-to-Digital Converter
TDA8768AH Analog-to-Digital Converter
TDA8760 10-bit high-speed analog-to-digital converter
TDA8761 9-bit analog-to-digital converter for digital video

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
INTEGRATED CIRCUITS DATA SHEET TDA8768 12-bit high-speed Analog-to-Digital Converter (ADC) Preliminary specification Supersedes data of 1998 Feb 25 File under Integrated Circuits, IC02 1998 Aug 26 Philips Semiconductors 12-bit high-speed Analog-to-Digital Converter (ADC) Preliminary specification TDA8768 FEATURES • 12-bit resolution • Sampling rate up to 55 MHz • −3 dB bandwidth of 190 MHz • 5 V power supplies • Binary or twos-complement CMOS outputs • In-range CMOS-compatible output • TLL-CMOS compatible static digital inputs • 3 to 5 V CMOS-compatible digital outputs • Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible • Power dissipation 325 mW (typical) • Low analog input capacitance (typical 2 pF), no buffer amplifier required • Integrated sample-and-hold a
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