TZA3015HW
Overview
- A-rabitte™(1): supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one single reference frequency
- 4-bit parallel interface
- Selectable Double Data Rate (DDR, half clock rate) or Single Data Rate (SDR) clocking scheme on parallel interface, enabling easy interfacing with FPGA devices
- I2C-bus and pin programmable
- Six selectable reference frequency ranges
- Transmitter, receiver and transceiver modes
- Clean-up loop back mode
- Line loop back mode
- Diagnostic loop back mode
- Serial loop timing mode
