Download UJA1023 Datasheet PDF
UJA1023 datasheet preview
UJA1023 page 2
Page 2
UJA1023 page 3
Page 3

UJA1023 Key Features

  • Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s and 20 kbit/s
  • Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor)
  • Eight bidirectional I/O pins
  • 4 × 2, 4 × 3, or 4 × 4 switch matrix to support reading and supplying a maximum
  • Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver
  • 8-bit ADC
  • Advanced low-power behavior
  • On-chip oscillator
  • Node Address (NAD) configuration via daisy chain or plug coding
  • Inputs supporting local wake-up and edge capturing

Related NXP Semiconductors Datasheets

Part Number Description
UJA1023T LIN-I/O slave
UJA1018 LIN transceiver
UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1065 High-speed CAN/LIN fail-safe system basis chip

UJA1023 Description

The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces basic ponents monly used in electronic control units for input and output handling. The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is LIN 2.0 / SAE J2602 pliant and LIN 1.3 patible, a 30 kΩ termination resistor necessary for LIN-slaves, and eight I/O ports which are configurable via the LIN bus. An...