74HC4515 Datasheet | NXP Semiconductors

Inverting outputs - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin patible with “4515” of the “4000B” series. They are specified in pliance with JEDEC standard no. 7A. 74HC/HCT4515 The 74HC/HCT4515 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 inverting outputs (Q0 to Q15) are mutually exclusive active LOW. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input (E) does not affect the state of the latch. When the “4515” is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL/ t PLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay An to Qn input capacitance power dissipation capacitance per package notes 1 and 2 .Data Sheet.net/ CONDITIONS HC CL = 15 p F; VCC = 5 V 25 3.5 44 HCT 26 3.5 46 UNIT ns p F p F September 1993 Datasheet pdf - http://..co.kr/ Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting PIN DESCRIPTION PIN NO. 1 2, 3, 21, 22 12 23 24 SYMBOL LE A0 to A3 GND E VCC 74HC/HCT4515 NAME AND...