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74HCT4520 - Dual 4-Bit Synchronous Binary Counter

This page provides the datasheet information for the 74HCT4520, a member of the 74HC4520 Dual 4-Bit Synchronous Binary Counter family.

Description

The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1).

They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR).

Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC4520: CMOS level.
  • For 74HCT4520: TTL level.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Multiple package options.
  • Specified from 40 C to +85 C and 40 C to +125 C 3.

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Datasheet preview – 74HCT4520

Datasheet Details

Part number 74HCT4520
Manufacturer NXP Semiconductors
File Size 162.98 KB
Description Dual 4-Bit Synchronous Binary Counter
Datasheet download datasheet 74HCT4520 Datasheet
Additional preview pages of the 74HCT4520 datasheet.

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Full PDF Text Transcription

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74HC4520; 74HCT4520 Dual 4-bit synchronous binary counter Rev. 3 — 4 December 2014 Product data sheet 1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes.
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