74LVC2G74 Datasheet - NXP Semiconductors

Single D-type flip-flop

74LVC2G74 Features

* I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: N HB

74LVC2G74 General Description

The 74LVC2G74 is a single positive-edge triggered D-type ﬂip-ﬂop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF circuitry disables the output.

74LVC2G74 Datasheet (153.62 KB)

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74LVC2G74

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NXP ↗ Semiconductors

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153.62 KB

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Single d-type flip-flop.
74LVC2G74 Rev. 06 23 December 2009 www.DataSheet4U.com Single D-type ﬂip-ﬂop with set and reset; positive edge trigger Product data sheet .

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74LVC2G74 Single D-type flip-flop NXP Semiconductors

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74LVC2G74 Features

74LVC2G74 General Description

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