NT5SV64M4BS Overview
These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an...
NT5SV64M4BS Key Features
- High Performance
- 5 133 MHz 7.5
- 5.4 ns ns ns
- Single Pulsed RAS Interface
- Fully Synchronous to Positive Clock Edge
- Four Banks controlled by BA0/BA1 (Bank Select)
