NT5DS64M4BF Datasheet | Nanya Techology

.. NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400A DDR400B (-5) (-5T) 200 200 200 166 - - - - - - - - - - - - - - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK...