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National Semiconductor Electronic Components Datasheet

74F299 Datasheet

Octal Universal Shift/Storage Register with Common Parallel I/O Pins

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May 1995
54F 74F299 Octal Universal Shift Storage Register
with Common Parallel I O Pins
General Description
The ’F299 is an 8-bit universal shift storage register with
TRI-STATE outputs Four modes of operation are possi-
ble hold (store) shift left shift right and load data The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins Additional outputs
Q0 – Q7 are provided to allow easy serial cascading A sep-
arate active LOW Master Reset is used to reset the register
Features
Y Common parallel I O for reduced pin count
Y Additional serial inputs and outputs for expansion
Y Four operating modes shift left shift right load and
store
Y TRI-STATE outputs for bus-oriented applications
Y Guaranteed 4000V minimum ESD protection
Commercial
74F299PC
74F299SC (Note 1)
74F299SJ (Note 1)
Military
54F299DM (Note 2)
54F299FM (Note 2)
54F299LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9515 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9515
TL F 9515 – 4
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F299 Datasheet

Octal Universal Shift/Storage Register with Common Parallel I/O Pins

No Preview Available !

Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9515 – 3
TL F 9515–2
Unit Loading Fan Out
Pin Names
CP
DS0
DS7
S0 S1
MR
OE1 OE2
I O0 – I O7
Q0 Q7
Description
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
TRI-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Serial Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 20
10 10
10 10
3 5 1 083
150 40(33 3)
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
70 mA b0 65 mA
b3 mA 24 mA (20 mA)
b1 mA 20 mA
Functional Description
The ’F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left shift right parallel load and hold operations The
type of operation is determined by S0 and S1 as shown in
the Mode Select Table All flip-flop outputs are brought out
through TRI-STATE buffers to separate I O pins that also
serve as data inputs in the parallel load mode Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops All other state changes are initiated
by the rising edge of the clock Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times relative to the rising edge of CP are
observed
A HIGH signal on either OE1 or OE2 disables the TRI-
STATE buffers and puts the I O pins in the high impedance
state In this condition the shift hold load and reset opera-
tions can still occur The TRI-STATE outputs are also dis-
abled by HIGH signals on both S0 and S1 in preparation for
a parallel load operation
Mode Select Table
Inputs
MR S1 S0 CP
Response
L X X X Asynchronous Reset Q0 – Q7 e LOW
xH H H L Parallel Load I On
Qn
x xH L H L Shift Right DS0
Q0 Q0
Q1 etc
x xH H L L Shift Left DS7
Q7 Q7
Q6 etc
H L L X Hold
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
2


Part Number 74F299
Description Octal Universal Shift/Storage Register with Common Parallel I/O Pins
Maker National
Total Page 10 Pages
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