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National Semiconductor Electronic Components Datasheet

74F373 Datasheet

Octal Transparent Latch with TRI-STATE Outputs

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May 1995
54F 74F373
Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’F373 consists of eight latches with TRI-STATE outputs
for bus organized system applications The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH
When LE is LOW the data that meets the setup times is
latched Data appears on the bus when the Output Enable
(OE) is LOW When OE is HIGH the bus output is in the high
impedance state
Features
Y Eight latches in a single package
Y TRI-STATE outputs for bus interfacing
Y Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Number
Package Description
74F373PC
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
54F373DM (QB) J20A
20-Lead Ceramic Dual-In-Line
74F373SC (Note 1)
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
74F373SJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
74F373MSA (Note 1)
MSA20
20-Lead Molded Shrink Small Outline EIAJ Type II
54F373FM (QB) W20A
20-Lead Cerpack
54F373LM (QB) E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment
for DIP SOIC SSOP and Flatpak
Pin Assignment
for LCC
TL F 9523–4
TL F 9523 – 2
TL F 9523 – 3
TL F 9523–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9523
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F373 Datasheet

Octal Transparent Latch with TRI-STATE Outputs

No Preview Available !

Unit Loading Fan Out
Pin Names
Description
D0 – D7
LE
OE
O0 – O7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Functional Description
The ’F373 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Truth Table
Inputs
LE OE
HL
HL
LL
XH
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance State
Dn
H
L
X
X
Logic Diagram
Output
On
H
L
On (no change)
Z
TL F 9523 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F373
Description Octal Transparent Latch with TRI-STATE Outputs
Maker National
Total Page 8 Pages
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