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National Semiconductor Electronic Components Datasheet

74F402 Datasheet

Serial Data Polynomial Generator/Checker

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January 1995
54F 74F402 Serial Data Polynomial
Generator Checker
General Description
The ’F402 expandable Serial Data Polynomial generator
checker is an expandable version of the ’F401 It provides
an advanced tool for the implementation of the most widely
used error detection scheme in serial digital handling sys-
tems A 4-bit control input selects one-of-six generator poly-
nomials The list of polynomials includes CRC-16 CRC-
CCITT and Ethernet as well as three other standard poly-
nomials (56th order 48th order 32nd order) Individual clear
and preset inputs are provided for floppy disk and other
applications The Error output indicates whether or not a
transmission error has occurred The CWG Control input
inhibits feedback during check word transmission The
’F402 is compatible with FAST devices and with all TTL
families
Features
Y Guaranteed 30 MHz data rate
Y Six selectable polynomials
Y Other polynomials available
Y Separate preset and clear controls
Y Expandable
Y Automatic right justification
Y Error output open collector
Y Typical applications
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Commercial
Military
Package
Number
Package Description
74F402PC
N16E
16-Lead (0 300 Wide) Molded Dual-In-Line
54F402DM (Note 1)
J16A
16-Lead Ceramic Dual-In-Line
54F402FM (Note 1)
W16A
16-Lead Cerpack
54F402LM (Note 1)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9535–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
Ethernet is a registered trademark of Xerox Corporation
C1995 National Semiconductor Corporation TL F 9535
TL F 9535 – 1
TL F 9535 – 2
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F402 Datasheet

Serial Data Polynomial Generator/Checker

No Preview Available !

Unit Loading Fan Out
Pin Names
S0 – S3
CWG
D CW
D
ER
RO
CP
SEI
RFB
MR
P
Open Collector
Description
Polynomial Select Inputs
Check Word Generate Input
Serial Data Check Word
Data Input
Error Output
Register Output
Clock Pulse
Serial Expansion Input
Register Feedback
Master Reset
Preset
UL
HIGH LOW
1 0 0 67
1 0 0 67
285(100) 13 3(6 7)
1 0 0 67
26 7(13 3)
285(100) 13 3(6 7)
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
54F 74F
Input IIH IIL
Output IOH IOL
20 mA b0 4 mA
20 mA b0 4 mA
b5 7 mA(b2 mA) 8 mA (4 mA)
20 mA b0 4 mA
16 mA (8 mA)
b5 7 mA(b2 mA) 8 mA (4 mA)
20 mA b0 4 mA
20 mA b0 4 mA
20 mA b0 4 mA
20 mA b0 4 mA
20 mA b0 4 mA
Functional Description
The ’F402 Serial Data Polynomial Generator Checker is an
expandable 16-bit programmable device which operates on
serial data streams and provides a means of detecting
transmission errors Cyclic encoding and decoding schemes
for error detection are based on polynomial manipulation in
modulo arithmetic For encoding the data stream (message
polynomial) is divided by a selected polynomial This divi-
sion results in a remainder (or residue) which is appended to
the message as check bits For error checking the bit
stream containing both data and check bits is divided by the
same selected polynomial If there are no detectable errors
this division results in a zero remainder Although it is possi-
ble to choose many generating polynomials of a given de-
gree standards exist that specify a small number of useful
polynomials The ’F402 implements the polynomials listed in
Table I by applying the appropriate logic levels to the select
pins S0 S1 S2 and S3
The ’F402 consists of a 16-bit register a Read Only Memory
(ROM) and associated control circuitry as shown in the
Block Diagram The polynomial control code presented at
inputs S0 S1 S2 and S3 is decoded by the ROM selecting
the desired polynomial or part of a polynomial by establish-
ing shift mode operation on the register with Exclusive OR
(XOR) gates at appropriate inputs To generate the check
bits the data stream is entered via the Data Inputs (D) us-
ing the LOW-to-HIGH transition of the Clock Input (CP) This
data is gated with the most significant Register Output (RO)
via the Register Feedback Input (RFB) and controls the
XOR gates The Check Word Generate (CWG) must be held
HIGH while the data is being entered After the last data bit
is entered the CWG is brought LOW and the check bits are
shifted out of the register(s) and appended to the data bits
(no external gating is needed)
To check an incoming message for errors both the data
and check bits are entered through the D Input with the
CWG Input held HIGH The Error Output becomes valid af-
ter the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP with the exception of the
Ethernet polynomial (see Applications paragraph) If no de-
tectable errors have occurred during the data transmission
the resultant internal register bits are all LOW and the Error
Output (ER) is HIGH If a detectable error has occurred ER
is LOW ER remains valid until the next LOW-to-HIGH tran-
sition of CP or until the device has been preset or reset
A HIGH on the Master Reset Input (MR) asynchronously
clears the entire register A LOW on the Preset Input (P)
asynchronously sets the entire register with the exception
of
1 The Ethernet residue selection in which the registers
containing the non-zero residue are cleared
2 The 56th order polynomial in which the 8 least significant
register bits of the least significant device are cleared
and
3 Register Se0 in which all bits are cleared
2


Part Number 74F402
Description Serial Data Polynomial Generator/Checker
Maker National
Total Page 12 Pages
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