Unit Loading Fan Out

Pin Names

S0 – S3

CWG

D CW

D

ER

RO

CP

SEI

RFB

MR

P

Open Collector

Description

Polynomial Select Inputs

Check Word Generate Input

Serial Data Check Word

Data Input

Error Output

Register Output

Clock Pulse

Serial Expansion Input

Register Feedback

Master Reset

Preset

UL

HIGH LOW

1 0 0 67

1 0 0 67

285(100) 13 3(6 7)

1 0 0 67

26 7(13 3)

285(100) 13 3(6 7)

1 0 0 67

1 0 0 67

1 0 0 67

1 0 0 67

1 0 0 67

54F 74F

Input IIH IIL

Output IOH IOL

20 mA b0 4 mA

20 mA b0 4 mA

b5 7 mA(b2 mA) 8 mA (4 mA)

20 mA b0 4 mA

16 mA (8 mA)

b5 7 mA(b2 mA) 8 mA (4 mA)

20 mA b0 4 mA

20 mA b0 4 mA

20 mA b0 4 mA

20 mA b0 4 mA

20 mA b0 4 mA

Functional Description

The ’F402 Serial Data Polynomial Generator Checker is an

expandable 16-bit programmable device which operates on

serial data streams and provides a means of detecting

transmission errors Cyclic encoding and decoding schemes

for error detection are based on polynomial manipulation in

modulo arithmetic For encoding the data stream (message

polynomial) is divided by a selected polynomial This divi-

sion results in a remainder (or residue) which is appended to

the message as check bits For error checking the bit

stream containing both data and check bits is divided by the

same selected polynomial If there are no detectable errors

this division results in a zero remainder Although it is possi-

ble to choose many generating polynomials of a given de-

gree standards exist that specify a small number of useful

polynomials The ’F402 implements the polynomials listed in

Table I by applying the appropriate logic levels to the select

pins S0 S1 S2 and S3

The ’F402 consists of a 16-bit register a Read Only Memory

(ROM) and associated control circuitry as shown in the

Block Diagram The polynomial control code presented at

inputs S0 S1 S2 and S3 is decoded by the ROM selecting

the desired polynomial or part of a polynomial by establish-

ing shift mode operation on the register with Exclusive OR

(XOR) gates at appropriate inputs To generate the check

bits the data stream is entered via the Data Inputs (D) us-

ing the LOW-to-HIGH transition of the Clock Input (CP) This

data is gated with the most significant Register Output (RO)

via the Register Feedback Input (RFB) and controls the

XOR gates The Check Word Generate (CWG) must be held

HIGH while the data is being entered After the last data bit

is entered the CWG is brought LOW and the check bits are

shifted out of the register(s) and appended to the data bits

(no external gating is needed)

To check an incoming message for errors both the data

and check bits are entered through the D Input with the

CWG Input held HIGH The Error Output becomes valid af-

ter the last check bit has been entered into the ’F402 by a

LOW-to-HIGH transition of CP with the exception of the

Ethernet polynomial (see Applications paragraph) If no de-

tectable errors have occurred during the data transmission

the resultant internal register bits are all LOW and the Error

Output (ER) is HIGH If a detectable error has occurred ER

is LOW ER remains valid until the next LOW-to-HIGH tran-

sition of CP or until the device has been preset or reset

A HIGH on the Master Reset Input (MR) asynchronously

clears the entire register A LOW on the Preset Input (P)

asynchronously sets the entire register with the exception

of

1 The Ethernet residue selection in which the registers

containing the non-zero residue are cleared

2 The 56th order polynomial in which the 8 least significant

register bits of the least significant device are cleared

and

3 Register Se0 in which all bits are cleared

2