Unit Loading Fan Out
Pin Names
Description
A0 – A3
D0 – D3
CS
OE
WE
CP
Q0 – Q3
Address Inputs
Data Inputs
Chip Select Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Clock Input (Outputs Change on
LOW-to-HIGH Transition)
TRI-STATE Outputs
UL
HIGH LOW
10 10
10 10
10 20
10 10
10 10
54F 74F
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
10 20
20 mA b1 2 mA
150 40 (33 3) b3 mA 24 mA (20 mA)
Functional Description
Write Operation When the three control inputs Write En-
able (WE) Chip Select (CS) and Clock (CP) are LOW the
information on the data inputs (D0 – D3) is written into the
memory location selected by the address inputs (A0 – A3) If
the input data changes while WE CS and CP are LOW the
contents of the selected memory location follow these
changes provided setup and hold time criteria are met
Block Diagram
Read Operation Whenever CS is LOW and CP goes from
LOW-to-HIGH the contents of the memory location select-
ed by the address inputs (A0 – A3) are edge-triggered into
the Output Register
The (OE) input controls the output buffers When OE is
HIGH the four outputs (Q0 – Q3) are in a high impedance or
OFF state when OE is LOW the outputs are determined by
the state of the Output Register
TL F 9538 – 4
2
