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National Semiconductor Electronic Components Datasheet

74F410 Datasheet

Register Stack16 x 4 RAM TRI-STATEE Output Register

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August 1995
54F 74F410 Register Stack 16 x 4 RAM
TRI-STATE Output Register
General Description
The ’F410 is a register-oriented high-speed 64-bit Read
Write Memory organized as 16-words by 4-bits An edge-
triggered 4-bit output register allows new input data to be
written while previous data is held TRI-STATE outputs are
provided for maximum versatility The ’F410 is fully compati-
ble with all TTL families
Features
Y Edge-triggered output register
Y Typical access time of 35 ns
Y TRI-STATE outputs
Y Optimized for register stack operation
Y 18-pin package
Y 9410 replacement
Commercial
Military
Package
Number
Package Description
74F410PC
N18A
18-Lead (0 300 Wide) Molded Dual-In-Line
54F410DM (Note 1)
J18A
18-Lead Ceramic Dual-In-Line
74F410SC
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
54F410LM
W20A
20-Lead Cerpak
Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP and SOIC
Pin Assignment
for LCC
TL F 9538–3
TL F 9538 – 1
TL F 9538 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9538
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F410 Datasheet

Register Stack16 x 4 RAM TRI-STATEE Output Register

No Preview Available !

Unit Loading Fan Out
Pin Names
Description
A0 – A3
D0 – D3
CS
OE
WE
CP
Q0 – Q3
Address Inputs
Data Inputs
Chip Select Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Clock Input (Outputs Change on
LOW-to-HIGH Transition)
TRI-STATE Outputs
UL
HIGH LOW
10 10
10 10
10 20
10 10
10 10
54F 74F
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
10 20
20 mA b1 2 mA
150 40 (33 3) b3 mA 24 mA (20 mA)
Functional Description
Write Operation When the three control inputs Write En-
able (WE) Chip Select (CS) and Clock (CP) are LOW the
information on the data inputs (D0 – D3) is written into the
memory location selected by the address inputs (A0 – A3) If
the input data changes while WE CS and CP are LOW the
contents of the selected memory location follow these
changes provided setup and hold time criteria are met
Block Diagram
Read Operation Whenever CS is LOW and CP goes from
LOW-to-HIGH the contents of the memory location select-
ed by the address inputs (A0 – A3) are edge-triggered into
the Output Register
The (OE) input controls the output buffers When OE is
HIGH the four outputs (Q0 – Q3) are in a high impedance or
OFF state when OE is LOW the outputs are determined by
the state of the Output Register
TL F 9538 – 4
2


Part Number 74F410
Description Register Stack16 x 4 RAM TRI-STATEE Output Register
Maker National
Total Page 8 Pages
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