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National Semiconductor Electronic Components Datasheet

74F544 Datasheet

Octal Registered Transceiver

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December 1994
54F 74F544
Octal Registered Transceiver
General Description
The ’F544 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direc-
tion Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow The
A outputs are guaranteed to sink 24 mA (20 mA Mil) while
the B outputs are rated for 64 mA (48 mA Mil) The ’F544
inverts data in both directions
Features
Y 8-bit octal transceiver
Y Back-to-back registers for storage
Y Separate controls for data flow in each direction
Y A outputs sink 24 mA (20 mA Mil) B outputs sink
64 mA (48 mA Mil)
Y 300 mil slim PDIP
Commercial
74F544SPC
74F544SC (Note 1)
74F544MSA (Note 1)
Military
54F544DM (Note 2)
54F544SDM (Note 2)
54F544FM (Note 2)
54F544LM (Note 2)
Package
Number
N24C
J24A
J24F
M24B
MSA24
W24C
E28A
Package Description
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead Ceramic Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Molded Shrink Small Outline EIAJ Type II
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and MSAX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9555 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9555
TL F 9555 – 1
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F544 Datasheet

Octal Registered Transceiver

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9555 – 4
TL F 9555–3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input IIH IIL
Output IOH IOL
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0 – A7
B0 – B7
A-to-B Output Enable Input (Active LOW) 1 0 1 0
20 mA b0 6 mA
B-to-A Output Enable Input (Active LOW) 1 0 1 0
20 mA b0 6 mA
A-to-B Enable Input (Active LOW)
10 20
20 mA b1 2 mA
B-to-A Enable Input (Active LOW)
10 20
20 mA b1 2 mA
A-to-B Latch Enable Input (Active LOW)
10 10
20 mA b0 6 mA
B-to-A Latch Enable Input (Active LOW)
10 10
20 mA b0 6 mA
A-to-B Data Inputs or
3 5 1 083
70 mA b650 mA
B-to-A TRI-STATE Outputs
150 40(33 3) b3 mA 24 mA (20 mA)
B-to-A Data Inputs or
3 5 1 083
70 mA b650 mA
A-to-B TRI-STATE Outputs
600 106 6(80) b12 mA 64 mA (48 mA)
Functional Description
The ’F544 contains two sets of eight D-type latches with
separate input and output controls for each set For data
flow from A to B for example the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A0 – A7 or
take data from B0 – B7 as indicated in the Data I O Control
Table With CEAB LOW a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs With CEAB and OEAB both
LOW the TRI-STATE B output buffers are active and re-
flect the data present at the output of the A latches Control
of data flow from B to A is similar but using the CEBA
LEBA and OEBA inputs
Data I O Control Table
Inputs
Latch Status Output Buffers
CEAB LEAB OEAB
HX X
Latched
XHX
Latched
L L X Transparent
XXH
LXL
High Z
High Z
Driving
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
A-to-B data flow shown B-to-A flow control is the same
except using CEBA LEBA and OEBA
2


Part Number 74F544
Description Octal Registered Transceiver
Maker National
Total Page 10 Pages
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