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National Semiconductor Electronic Components Datasheet

74F573 Datasheet

Octal D-Type Latch with TRI-STATE Outputs

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August 1995
54F 74F573
Octal D-Type Latch with TRI-STATE Outputs
General Description
The ’F573 is a high speed octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable
(OE) inputs
This device is functionally identical to the ’F373 but has
different pinouts
Features
Y Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Y Useful as input or output port for microprocessors
Y Functionally identical to ’F373
Y TRI-STATE outputs for bus interfacing
Y Guaranteed 4000V minimum ESD protection
Commercial
74F573PC
74F573SC (Note 1)
74F573SJ (Note 1)
Military
54F573DM (Note 2)
54F573FM (Note 2)
54F573LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpak
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9566–1
IEEE IEC
TL F 9566 – 2
TL F 9566 – 3
TL F 9566–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9566
RRD-B30M115 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F573 Datasheet

Octal D-Type Latch with TRI-STATE Outputs

No Preview Available !

Unit Loading Fan Out
Pin Names
Description
D0 – D7
LE
OE
O0 – O7
Data Inputs
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
TRI-STATE Latch Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
10 10
20 mA b0 6 mA
150 40(33 3) b3 mA 24 mA (20 mA)
Functional Description
The ’F573 contains eight D-type latches with 3-state output
buffers When the Latch Enable (LE) input is HIGH data on
the Dn inputs enters the latches In this condition the latch-
es are transparent i e a latch output will change state each
time its D input changes When LE is LOW the latches store
the information that was present on the D inputs a setup
time preceding the HIGH-to-LOW transition of LE The 3-
state buffers are controlled by the Output Enable (OE) input
When OE is LOW the buffers are in the bi-state mode
When OE is HIGH the buffers are in the high impedance
mode but this does not interfer with entering new data into
the latches
Function Table
Inputs
OE LE D
L HH
L HL
L LX
H XX
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
O0 e Value stored from previous clock cycle
Logic Diagram
Outputs
O
H
L
O0
Z
TL F 9566 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F573
Description Octal D-Type Latch with TRI-STATE Outputs
Maker National
Total Page 8 Pages
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