* Y Y Y Y Y Y Y Y Y Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output high impedance state does not impede any other mode of operation 8-bit I O pins are TRI-STATE buffers Typical shift frequency is
DM74LS962 Datasheet (157.99 KB)
DM74LS962
National
157.99 KB
Dual rank 8-bit tri-state shift register.
DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register August 1991 DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register General Desc.
📁 Related Datasheet
DM74LS96 5 Bit Shift Registers (National)
DM74LS90 Decade and Binary Counters (National)
DM74LS90 Decade and Binary Counters (Fairchild Semiconductor)
DM74LS90M Decade and Binary Counters (Fairchild Semiconductor)
DM74LS90M Decade and Binary Counters (National Semiconductor)
DM74LS90N Decade and Binary Counters (National Semiconductor)
DM74LS90N Decade and Binary Counters (Fairchild Semiconductor)
DM74LS93 Decade and Binary Counters (National)
DM74LS93 Decade and Binary Counters (Fairchild Semiconductor)
DM74LS93M Decade and Binary Counters (National Semiconductor)
