* complementary outputs from each flip-flop Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of
54175
National Semiconductor
150.38 KB
Hex/quad d flip-flops with clear.
54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear June 1989 54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-F.
📁 Related Datasheet
5417 High Voltage Open-Collector Outputs (National Semiconductor)
54170 4 x 4 Register File (National Semiconductor)
54173 TRI-STATE Quad Registers (National Semiconductor)
54174 Hex/Quad D Flip-Flops with Clear (National Semiconductor)
541 HIGH POWER OP-AMP (ETC)
5410 VCXO (NPC)
5410 Triple 3-Input NAND Gates (National Semiconductor)
54109 Dual J-K Positive-Edge-Triggered Flip-Flops (Texas Instruments)
5410CR EL5410CR (ETC)
5412 Triple 3-Input NAND Gate (Fairchild Semiconductor)
