hex/quad d flip-flops with clear.
complementary outputs from each flip-flop Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing ed.
include Buffer storage registers Shift registers Pattern generators Typical clock frequency 40 MHz Typical power dissipa.
These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) version features complementary outputs from each flip-flop Information at the D inputs meeting the set.
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