Datasheet4U Logo Datasheet4U.com

54AC273 - Octal D Flip-Flop

Description

The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Features

  • n n n n n n n n n n Ideal buffer for microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous master reset See ’377 for clock enable version See ’373 for transparent latch version See ’374 for TRI-STATE ® version Outputs source/sink 24 mA ’ACT has TTL-compatible inputs Standard Military Drawing (SMD).
  • ’AC273: 5962-87756 Logic Symbols IEEE/IEC DS100288-1 DS100288-2 Pin Names D0.
  • D7 MR CP Q0.
  • Q7.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
54AC241 Octal Buffer/Line Driver Texas Instruments
54AC244-N Octal Buffer/Line Driver Texas Instruments
54AC251 8-Input Multiplexer Texas Instruments
54AC257 Quad 2-Input Multiplexer Texas Instruments
54AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES Texas Instruments

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
54AC20 Dual 4-Input NAND Gate
54AC240 Octal Buffer/Line Driver
54AC241 Octal Buffer/Line Driver
54AC244 Octal Buffer/Line Driver
54AC245 Octal Bidirectional Transceiver

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com 54AC273 Octal D Flip-Flop 54AC273 July 1998 54AC273 Octal D Flip-Flop General Description The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Published: |