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54ACQ374 Datasheet

Quiet Series Octal D Flip-Flop

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August 1998
54ACQ374 54ACTQ374
Quiet Series Octal D Flip-Flop with TRI-STATE® Outputs
General Description
The ’ACQ/’ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and TRI-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered positive edge-triggered clock
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT374
n 4 kV minimum ESD immunity
n Standard Military Drawing (SMD)
— ’ACTQ374: 5962-92189
— ’ACQ374: 5962-92179
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
and Flatpak
IEEE/IEC
DS100239-1
DS100239-3
Pin Assignment for LCC
DS100239-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100239
DS100239-4
www.national.com


National Semiconductor Electronic Components Datasheet

54ACQ374 Datasheet

Quiet Series Octal D Flip-Flop

No Preview Available !

Connection Diagrams (Continued)
Pin Names
D0– D7
CP
OE
O0– O7
Description
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
Functional Description
The ’ACQ/’ACTQ374 consists of eight edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation
of the OE input does not affect the state of the flip-flops.
Truth Table
Inputs
Dn CP
HN
LN
XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
Logic Diagram
OE
L
L
H
Outputs
On
H
L
Z
DS100239-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2


Part Number 54ACQ374
Description Quiet Series Octal D Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
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