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National Semiconductor Electronic Components Datasheet

54ACQ573 Datasheet

Quiet Series Octal Latch

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August 1998
54ACQ573 54ACTQ573
Quiet Series Octal Latch with TRI-STATE® Outputs
General Description
The ’ACQ/’ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common Out-
put Enable (OE) inputs. The ’ACQ/’ACTQ573 is functionally
identical to the ’ACQ/’ACTQ373 but with inputs and outputs
on opposite sides of the package. The ’ACQ/’ACTQ utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Seriesfeatures GTOoutput control and un-
dershoot corrector in addition to a split ground bus for supe-
rior performance.
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n Outputs source/sink 24 mA
n Faster prop delays than standard ’ACT573
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD)
— ’ACTQ573: 5962-92194
— ’ACQ573: 5962-92180
Features
n ICC and IOZ reduced by 50%
Logic Symbols
IEEE/IEC
DS100242-1
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
DS100242-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100242
www.national.com


National Semiconductor Electronic Components Datasheet

54ACQ573 Datasheet

Quiet Series Octal Latch

No Preview Available !

Connection Diagrams
Pin Assignment for DIP
and Flatpak
DS100242-3
Pin Assignment for LCC
Logic Diagram
DS100242-4
Functional Description
The ’ACQ/’ACTQ573 contains eight D-type latches with
TRI-STATE output buffers. When the Latch Enable (LE) in-
put is HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high im-
pedance mode but this does not interfere with entering new
data into the latches.
Truth Table
Inputs
Outputs
OE LE D
L HH
On
H
L HL
L
L LX
H XX
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
DS100242-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2


Part Number 54ACQ573
Description Quiet Series Octal Latch
Maker National Semiconductor
Total Page 8 Pages
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