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National Semiconductor Electronic Components Datasheet

54ACT175 Datasheet

Quad D Flip-Flop

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54ACT175 pdf
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August 1998
54AC175 54ACT175
Quad D Flip-Flop
General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-
vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in-
puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro-
vided. A Master Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.
n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC175: 5962-89552
— ’ACT175: 5962-89693
Features
n Edge-triggered D-type inputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
IEEE/IEC
DS100278-1
DS100278-3
Pin Assignment for LCC
DS100278-2
Pin Names
D0– D3
CP
MR
Q0– Q3
Q0– Q3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100278
DS100278-4
www.national.com


National Semiconductor Electronic Components Datasheet

54ACT175 Datasheet

Quad D Flip-Flop

No Preview Available !

54ACT175 pdf
Functional Description
The ’AC/’ACT175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or Data
inputs. The ’AC/’ACT175 is useful for general logic applica-
tions where a common Master Reset and Clock are
acceptable.
Logic Diagram
Truth Table
Inputs
@ tn, MR = H
Dn
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Outputs
@ tn+1
Qn Qn
LH
HL
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
DS100278-5
www.national.com
2


Part Number 54ACT175
Description Quad D Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
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