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National Semiconductor Electronic Components Datasheet

54ACT299 Datasheet

8-Input Universal Shift/Storage Register

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September 1998
54AC299 54ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
General Description
The ’AC/’ACT299 is an 8-bit universal shift/storage register
with TRI-STATE® outputs. Four modes of operation are pos-
sible: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins. Additional outputs
are provided for flip-flops Q0, Q7 to allow easy serial cascad-
ing. A separate active LOW Master Reset is used to reset the
register.
Features
n ICC and IOZ reduced by 50%
n Common parallel I/O for reduced pin count
n Additional serial inputs and outputs for expansion
n Four operating modes: shift left, shift right, load and
store
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT299 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
’AC299: 5962-88754
’ACT299: 5962-88771
Ordering Code:
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
IEEE/IEC
DS100252-1
DS100252-2
Pin Assignment for LCC
DS100252-4
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100252
DS100252-3
www.national.com


National Semiconductor Electronic Components Datasheet

54ACT299 Datasheet

8-Input Universal Shift/Storage Register

No Preview Available !

Connection Diagrams (Continued)
Pin Names
CP
DS0
DS7
S0, S1
MR
OE1, OE2
I/O0–I/O7
Q0, Q7
Description
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
TRI-STATE Output Enable Inputs
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Serial Outputs
Functional Description
The ’AC/’ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S0 and S1, as
shown in the Truth Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7 are
also brought out on other pins for expansion in serial shifting
of longer words.
A LOW signal on MR overrides the Select and CP inputs and
resets the flip-flops. All other state changes are initiated by
the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE1 or OE2 disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S0 and S1 in preparation for a parallel load
operation.
Truth Table
Inputs
MR S1 S0 CP
LXXX
H H HN
H L HN
H H LN
HL LX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Response
Asynchronous Reset;
Q0–Q7 = LOW
Parallel Load; I/On Qn
Shift Right; DS0 Q0,
Q0 Q1, etc.
Shift Left, DS7 Q7,
Q7 Q6, etc.
Hold
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2


Part Number 54ACT299
Description 8-Input Universal Shift/Storage Register
Maker National Semiconductor
Total Page 10 Pages
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