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54ACT377 - Octal D Flip-Flop

Download the 54ACT377 datasheet PDF. This datasheet also covers the 54AC377 variant, as both devices belong to the same octal d flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered.

Key Features

  • n ICC reduced by 50% Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names D0.
  • D7 CE Q0.
  • Q7 CP.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (54AC377_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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54ACT11010 Triple 3-Input Positive-NAND Gates Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
54ACT373 Octal Transparent Latch
54ACT374 Octal D Flip-Flop
54ACT00 Quad 2-Input NAND Gate
54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable February 1999 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.