900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




National Semiconductor Electronic Components Datasheet

54ACT825 Datasheet

8-Bit D Flip-Flop

No Preview Available !

February 1999
www.DataSheet4U.com
54ACT825
8-Bit D Flip-Flop
General Description
The ’ACT825 is an 8-bit buffered register. They have Clock
Enable and Clear features which are ideal for parity bus in-
terfacing in high performance microprogramming systems.
Also included are multiple enables that allow multi-use con-
trol of the interface. The ’ACT825 has noninverting outputs
and is fully compatible with AMD’s Am29825.
Features
n Outputs source/sink 24 mA
n Inputs and outputs are on opposite sides
n ’ACT825 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’ACT825: 5962-91611
Logic Symbols
IEEE/IEC
DS100254-1
Pin Names
D0– D7
O0– O7
OE1, OE2, OE3
EN
CLR
CP
Description
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
DS100254-3
FACTis a trademark of Fairchild Semiconductor.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100254
www.national.com


National Semiconductor Electronic Components Datasheet

54ACT825 Datasheet

8-Bit D Flip-Flop

No Preview Available !

Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment for LCC
www.DataSheet4U.com
DS100254-2
DS100254-4
Functional Description
The ’ACT825 consists of eight D-type edge-triggered
flip-flops. These devices have TRI-STATE® outputs for bus
systems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW,
the contents of the flip-flops are available at the outputs.
When one of OE1, OE2 or OE3 is HIGH, the outputs go to the
high impedance state.
Operation of the OE input does not affect the state of the
flip-flops. The ’ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
OE CLR EN
HX L
HX L
HLX
LLX
HHH
L HH
HH L
HH L
LHL
LHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
CP
N
N
X
X
X
X
N
N
N
N
Dn
L
H
X
X
X
X
L
H
L
H
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
www.national.com
2


Part Number 54ACT825
Description 8-Bit D Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
PDF Download

54ACT825 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 54ACT821 10-Bit D Flip-Flop
National Semiconductor
2 54ACT823 9-Bit D Flip-Flop
National Semiconductor
3 54ACT825 8-Bit D Flip-Flop
National Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy