54F377 Datasheet - National Semiconductor

Octal D Flip-Flop

54F377 Features

* Y Ideal for addressable register applications Y Clock enable for address and data synchronization applications Y Eight edge-triggered D flip-flops Y Buffered common clock Y See ’F273 for master reset version Y See ’F373 for transparent latch version Y See ’F374 for TRI-STATE version Y Guaranteed 400

54F377 General Description

The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH .

54F377 Datasheet (339.13 KB)

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54F377

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National Semiconductor

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339.13 KB

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Octal d flip-flop.

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54F377 Octal Flip-Flop National Semiconductor

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54F377 Features

54F377 General Description

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